1. Field of the Invention
The present invention relates to an improved pattern distortion detecting method and apparatus that are applied to pattern formation in a semiconductor manufacturing process, as well as to a recording medium on which a program to be used for performing such pattern distortion detection by using a computer is recorded.
2. Background Art
At present, the design rules of semiconductor devices have reached the 0.15-xcexcm level and this value is smaller than light source wavelengths (0.248 xcexcm in the case of using an excimer laser) of steppers for transfer of such patterns. Since the resolution performance deteriorates significantly in this circumstance, it is attempted to improve the resolution performance by using a special transfer technique such as a modified illumination technique.
Where such a special transfer technique is used, the pattern fidelity deteriorates though the resolution performance is improved. Also in other processes such as an etching process, variations in pattern dimensions may occur owing to differences in the density of miniaturized patterns.
To solve the above problems, the OPC (Optical Proximity Effect Correction) is widely employed which modifies design layout patterns so as to obtain desired patterns. It is assumed here that the OPC means the method to correct pattern distortions in general that result from not only optics-related causes but also process-related ones.
The OPC is classified into three kinds of methods. The first method is a model-based OPC in which patterns are modified based on simulation results. The second method is a rule-based OPC in which rules (OPC rules) according to which to modify design layout patterns are set in advance in consideration of geometrical features of the design layout patterns such as widths of respective patterns, distances between adjacent patterns, and distances from corner portions, and the design layout patterns are modified according to those rules. The third method is a combination of the first and second methods.
The pattern distortion detection for checking whether desired finish patterns will be obtained correctly by using OPC results is important.
In all of the above processes except the rule-based OPC, it is necessary to perform a simulation by using, as an input, design layout patterns or post-OPC patterns.
FIG. 20 shows the configuration of a conventional pattern distortion detecting apparatus. In FIG. 20, a layout pattern holding section 1 stores layout patterns to be used for prediction of pattern distortions. An on-edge sampling point generation rule holding section 7 holds rules according to which to generate sampling points on pattern edges of layout patterns. An on-edge sampling point generating means 2 generates sampling points on pattern edges. A pattern distortion predicting means 3 predicts pattern distortion amounts by performing simulations for the respective generated sampling points. A pattern distortion correcting means 4 corrects the layout patterns in accordance with the predicted pattern distortion amounts. Processing results are output to a pattern distortion information holding section 5 and/or a corrected layout pattern holding section 6.
When pattern distortion detection is performed by using the above conventional pattern distortion detecting apparatus, the processes from the layout pattern holding section 1 to the pattern distortion predicting means 3 are executed and, as a result, pattern distortion information is obtained in the pattern distortion information holding section 5. When a pattern distortion correction is performed, the processes from the layout pattern holding section 1 to the pattern distortion correcting means 4 are executed and, as a result, corrected layout patterns are obtained in the corrected layout pattern holding section 6.
Next, the operation of the conventional pattern distortion detecting apparatus, that is, a conventional pattern distortion detecting method, will be described.
FIG. 21 is a flowchart of the conventional pattern distortion detecting method.
Steps 21-23 shown in FIG. 21 are executed for a pattern distortion check and steps 21-22 and 24-26 are executed for a pattern distortion correction. All the steps are executed when both are needed.
First, at step 21 shown in FIG. 21, sampling points are generated on the edge portion of a layout pattern stored in the layout pattern holding section 1 according to on-edge sampling point generation rules that are stored in the on-edge sampling point generation rule holding section 7 shown in FIG. 20. The sampling point generation rules will be described later.
At step 22, a pattern to be generated from the layout pattern is simulated for the respective sampling points and pattern distortion amounts are thereby calculated. At step 23, pattern distortion information is output to the pattern distortion information holding section 5 shown in FIG. 20.
At step 24, the pattern is modified so as to cancel out the pattern distortion amounts calculated at step 22. The most typical method is to move the pattern edge in the direction opposite to the direction of the pattern distortion by the pattern distortion amounts. (There is a method in which after the pattern edge is moved by a predetermined amount at the first attempt, corrections and checks (the checking method will be described below) are repeated.)
At step 25, to detect whether the correction has been made correctly, it is judged whether to re-execute steps 22-24. Usually, a judgment criterion is set such that the process is to proceed to step 26 if the number of iterations of steps 22-24 has exceeded a predetermined number or the pattern distortion amounts have fallen within a specified value.
At step 26, a corrected pattern is output to the corrected layout pattern holding section 6 shown in FIG. 20.
The conventional pattern distortion check and correction are performed according to the above process.
A specific example of a conventional sampling point generation method will be described below. The sampling point generation is important in the present invention.
FIG. 22 shows an example in which sampling points are set all over an input layout pattern to be simulated and simulations are performed for the respective sampling points. In FIG. 22, a layout pattern 1 is hatched and sampling points 3 are indicated by mark xe2x80x9cx.xe2x80x9d Reference symbol 1a denotes pattern edges. This method has a problem of a very long processing time because calculations need to be performed for an enormous number of sampling points.
In view of the above, as shown in FIG. 23, it is a common practice to set sampling points 3 only on the pattern edges 1a that greatly affect the accuracy of pattern dimensions, whereby the number of sampling points is reduced and the calculation time is shortened.
FIG. 24 shows sampling points that are set in a case where a plurality of layout patterns exist. In FIG. 24, reference symbol 1 denotes a layout pattern; 1a, its pattern edges; 3, sampling points; 7, a layout pattern in another layer; and 8, another layout pattern in the same layer as the layout pattern 1.
In this manner, it is attempted to further reduce the number of sampling points and increase the processing speed by setting the sampling points 3 on the pattern edges 1a selectively in accordance with presence/absence of the adjacent layout pattern 8 and the layout pattern 7 in another layer and conditions relating to corners etc. and causing simulation results of the sampling points 3 to represent values of the entire edges.
However, the above conventional method cannot detect and correct a pattern distortion in a portion distant from a pattern edge that occurs, for example, in a halftone mask or in the case of an abnormally large pattern distortion.
FIG. 25 shows a specific example ofa halftone mask (described later in detail). In FIG. 25, reference numeral 1 denotes layout patterns and 9 denotes a pattern distortion in a portion distant from edge portions 1a. It is known that a pattern distortion like the pattern distortion 9 can be corrected by generating a figure that is smaller in size than a resolution limit in the pattern distortion portion. A figure that is generated in such a situation may be an opaque portion or a transparent portion.
As described above, although the conventional method can detect a pattern distortion by setting sampling points on pattern edges, it cannot detect a pattern distortion in a portion distant from a pattern edge, for example, it cannot detect and correct a pattern distortion in a portion distant from a pattern edge that occurs, for example, in a halftone mask or in the case of an abnormally large pattern distortion.
The present invention has been made to solve the above problems in the art, and relates to a pattern distortion detecting apparatus and a pattern distortion correcting apparatus which detect and correct, respectively, a portion where a pattern distortion occurs by predicting a pattern distortion that will occur in a pattern forming process such as a photolithography or etching process executed in semiconductor manufacture and checking differences between a predicted layout pattern and a design layout pattern. An object of the invention is to make it possible to predict, at high speed, pattern distortion amounts in a portion other than the pattern edges and detect and correct a pattern distortion in a portion other than the pattern edges by setting sampling points selectively also in portions other than the pattern edges.
FIGS. 26(a) and 26(b) illustrate a conventional VTR (Variable Threshold Resist) model. In FIG. 26(a), reference symbol 1 denotes a layout pattern, 1a denotes a pattern edge, and 3 denotes a sampling point. In FIG. 26(b), the horizontal axis represents the position on a line segment that intersects the pattern edge 1a at the sampling point 3 and the vertical axis represents a physical quantity in pattern formation.
As shown in FIGS. 26(a) and 26(b), in the VTR model, the pattern distortion amount in the pattern edge portion is calculated at the sampling point 3 in accordance with the gradient of a process quantity such as optical intensity. Therefore, gradient calculation points 9 for a simulation are set in the vicinity of the sampling point 3 on the pattern edge 1a. This is to determine the pattern distortion amount on the pattern edge 1a more accurately by calculating a gradient.
The invention is much different from the conventional method in that sampling points are set selectively in a portion distant from an edge to calculate a process quantity such as optical intensity in a portion other than the edge portion. That is, in the present invention, where the VTR model is used, calculations are performed by setting gradient calculation points additionally in the vicinity of a sampling point that is set in a portion other than an edge portion.
According to one aspect of the present invention, in a pattern distortion detecting method, sampling points are selectively generated in a prescribed portion other than a pattern edge portion of a layout pattern used in a semiconductor manufacturing process based on an input that is data of the layout pattern. Simulation results for the respective sampling points are obtained regarding a pattern to be generated from the layout pattern. Then, pattern distortion amounts for the respective sampling points are detected in the portion other than the pattern edge portion by comparing the data of the layout pattern and the simulation results.
In another aspect of the invention, further a corrected layout pattern is generated by correcting the layout pattern based on the detected pattern distortion amounts.
According to another aspect of the present invention, a pattern distortion detecting apparatus conducting the above mentioned method is provided.
Further, according to another aspect of the present invention, a computer-readable recording medium is provided on which a program is recorded for causing a computer to execute the above mentioned method.
Other and further objects, features and advantages of the invention will appear more fully from the following description.